1. Field of the Invention
The invention relates to a clock synchronization mechanism, more particularly to a method and system for clock synchronization of semiconductor devices, which uses a master-slave configuration in conjunction with a phase checker, such that semiconductor devices synchronize the clocks and thus precisely output clock demands to ensure reliability during operation.
2. Description of the Related Art
At present, for clock synchronization, most designs focus on a single chip, as described in U.S. Pat. No. 5,999,025 and U.S. Pat. No. 6,304,582. The former (U.S. Pat. No. 5,999,025) essentially describes a synchronization of an external clock and an on-chip voltage controlled oscillator (VCO) clock. The latter (U.S. Pat. No. 6,304,582) essentially describes a synchronization of an oscillator clock and clocks in a chip. As cited, these clock synchronization means for multiple chips lack effectiveness with semiconductor devices in which delay locked loop (DLL) or digital clock manager (DCM) is used as a clock source.